This application relies for priority upon Korean Patent Application No. 98-10517, filed on Mar. 26, 1998, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a method for manufacturing a nonvolatile memory device. More particularly, the present invention relates to a method for manufacturing a NOR flash memory device having a stacked gate structure of a floating gate and a control gate.
Semiconductor memory devices are largely divided into Random Access Memories (RAMs), such as Dynamic RAMs (DRAMs) and Static RAMs (SRAMs), and Read Only Memories (ROMs), including Programmable ROMs (PROMs), (Erasable PROMs (EPROMs), and Electrically Erasable PROMs (EEPROMs). RAMs are referred to as volatile memories in that data contained in them is destroyed with the passage of time. In contrast, ROMS are non-volatile memory and retain data once it is entered. Among such ROMs, demands for EEPROMs (Electrically Erasable and Programmable ROMs) are increasing. The EEPROM cells, or the flash memory cells, have a stacked gate structure including a floating gate and a control gate.
Flash memory cells are divided into a NOR type and a NAND type. In the NAND type, which is useful for realizing high integration, unit strings, each containing n cells connected in series, are connected in parallel between bit lines and ground lines. In the NOR type, which allows high-speed operation, individual cells are connected in parallel between bit lines and ground lines.
A description of the structure and operation of a basic NOR flash memory cell, disclosed in IEDM""85, pp. 616xcx9c619, xe2x80x9cA Single Transistor EPROM Cell And Its Implementation In A 512K CMOS EEPROMxe2x80x9d, will be given below with reference to FIGS. 1 to 3.
FIG. 1 is a partial layout diagram of a memory cell array in a conventional NOR flash memory device, FIG. 2 is an equivalent circuit diagram of the memory cell array of FIG. 1, and FIG. 3 is a cross-sectional view of a unit cell. Reference numeral 10 denotes a semiconductor substrate; reference numeral 11 denotes an active source region; reference no numeral 14 denotes a tunnel oxide film; reference numeral 16 denotes a floating gate; reference numeral 18 denotes an interpoly dielectric layer; reference numeral 20 denotes a control gate, reference numerals 24a and 24b denote source and drain regions, respectively; and reference numeral 28 denotes a bit line contact.
Referring to FIGS. 1 to 3, a memory cell array has a plurality of bit lines B/L arranged at specified intervals, a plurality of word lines W/L and a plurality of source lines CSL. A unit cell in the array contains a stacked gate structure including the floating gate 16 and the control gate 20. Each unit cell is formed in an area where the word line W/L perpendicularly intersects one of the metal bit lines B/L. Two individual cells are connected to the bit line B/L by a single bit line contact 28, and the active source region 11 formed of an impurity layer and disposed in parallel with the word line W/L, is connected by the source line CSL arranged in parallel with the bit line B/L for tens of bits.
In a unit cell, the he tunnel oxide film 14 is interposed between the floating gate 16 and the substrate 10, and the interpoly dielectric layer 18 is interposed between the floating gate 16 and the control gate 20. The source and drain regions 24a and 24b are formed in the surface of the substrate 10 in self-alignment with the stacked gate. The floating gate 16 extends across an active region and portions of the edges of field regions at both sides of the active region, thus being isolated from that of an adjacent cell. The control gate 20 is connected to that of an adjacent cell, thus forming a word line W/L.
Adjacent cells are formed in opposite directions, sharing the source/drain regions 24a and 24b. The drain region 24b of a unit cell is connected to that of an adjacent cell in the same row, and has the bit line contact 28 formed therein. Bit line contacts 28 in the same row are electrically connected by the bit line B/L perpendicular to the word line W/L. That is, two cells are connected to the bit line B/L by a single bit line contact 28.
The source region 24a of the unit cell is connected to that of an adjacent cell in the same column through the active source region 11 formed of an impurity diffusion layer parallel to the word line W/L. In addition, to reduce the resistance of the source line, a single source line contact is formed in the active source region 11 parallel to the word line W/L, for a plurality of bit lines B/L. The source line CSL parallel to the bit line B/L is electrically connected to the active source region 11 through the source line contact 29.
Such a general NOR flash memory cell is programmed by CHE (channel hot electron) injection and erased through a source or a bulk substrate by Fowler-Nordheim tunneling (F-N tunneling).
For a programming operation, the threshold voltage Vth of a cell is increased from an initial level of about 2V, to about 7V by storing electrons on the floating gate 16. In other words, by applying 6xcx9c7V to the selected bit line B/L, 10xcx9c12V to the selected word line W/L, and 0V to the source and the bulk substrate, parts of the CHEs are introduced onto the floating gate 16 via the tunnel oxide film 18 by a gate electric field. In this way, the cell is programmed.
For an erasing operation, the threshold voltage Vth of the cell is dropped to the initial level, i.e., about 2V, by removing electrons from the floating gate 16. In other words, by floating the selected bit line B/L and applying 12xcx9c15V to the source and 0V to the selected word line W/L, the electrons are removed from the floating gate 16 to the source junction via the tunnel oxide film 18 of about 100 xc3x85 by Fowler-Nordheim tunneling, due to a potential difference between the floating gate 16 and the source junction. Typically, since the source junctions of all cells are electrically connected to one by the active source region 11, cells are collectively erased in block units each block being hundreds to thousands of bits. Furthers since the source voltage during the erasing operation is higher than the drain voltage during the programming operation, the source junction is formed to be a double diffused junction (hereinafter referred to as a xe2x80x9cDDxe2x80x9d) structure as shown in FIG. 3 so as to make the source junction have higher breakdown voltage than the drain junction.
A reading operation determines the presence or absence of a current path through erased and programmed cells by applying about 1V to the selected bit line B/L and 4xcx9c5V to the word line W/L.
The source line CSL serves to discharge to a ground node the great amounts of current generated by the cells during programming and reading operations. To discharge large amount of current in a short time in the flash memory cell using CHE injection, one source line CSL is formed for every 16xcx9c32 bits.
During the programming and erasing operations, the F-N tunneling characteristics or the hot electron generation efficiency may be varied according to the dimension of the cell. In particular if the cell size is reduced, as it is with highly integrated devices, the loss of efficiency can become serious. For example, in the case of a cell having a short channel length, the punching characteristics between the source and the drain become degraded, while the hot electron generation efficiency is increased by the increase of cell current during a programming operation, thus allowing short programming time. Furthermore, when the overlap area between the source junction and the floating gate is increased during the source erasing operation, the voltage Vf induced at the floating gate when a source voltage Vs is applied is given by
Vf=(Cs/Ct)Vsxe2x80x83xe2x80x83(1)
where Cs is an overlap capacitance between the source junction and the floating gate and Ct is a total capacitance, i.e., xe2x80x9cCs+Cb+Cfxe2x80x9d where Cb is an overlap capacitance between a bulk substrate and the floating gate, and Cf is an overlap capacitance between the floating gate and the control gate. Hence, if Cs is increased, Vf is also increased and thus the electric field between both ends of the tunnel oxide film required in F-N tunneling is decreased, resulting in an increase in the required erasing time.
FIG. 4 is a layout diagram showing a misalignment between the active source region and the word line in the above-described conventional NOR flash memory device. FIGS. 5A and 5B are sectional views of the conventional NOR flash memory cell, taken along lines A1-A1xe2x80x2 and A2-A2xe2x80x2 of FIG. 4, respectively.
In the conventional NOR flash memory device as described above, the active source region 11 is formed in the form of xe2x80x9cxe2x8axa5xe2x80x9d so as to be connected to an adjacent cell, as can be seen from the layout of FIG. 1. If a misalignment occurs between the word line and the active source region 11 when patterning the word line 20 as shown by b of FIG. 4, the overlap area between the source junction 24a and the floating gate 16 in a specific cell is increased as shown in FIG. 5B and thereby the overlap capacitance between the source junction 24a and the floating gate 16 is also increased. To prevent this problem, the distance between the active source region 11 and the word line 20 should be increased as shown in FIG. 1. However, the increase in distance between the active source region 11 and the word line 20 causes a corresponding increase in cell size, making such a layout is inadequate for the highly integrated memory cells.
A method for improving this problem is disclosed in U.S. Pat. No. 5,470,773 FIG. 6 shows a layout of a memory cell array of the NOR flash memory device according to this method. In FIG. 6, reference numeral 51 denotes an active region, reference numeral 56 denotes a floating gate, reference numeral 58 denotes a control gate and reference numeral 72 denotes a bit line contact.
Referring now to FIG. 6, since the active region 51 is arranged to be a straight line parallel to the bit line B/L, the source regions of adjacent cells in the word line direction cannot be connected to each other. Hence, after opening the region xe2x80x9cBxe2x80x9d of FIG. 6 by photolithography, the field oxide film formed on the region B is etched, the exposed substrate is implanted with impurity, the implanted impurity is diffused by a thermal process, thereby forming an impurity diffusion region which is connected to the source region of an adjacent cell, to achieve a common source region. The common source region formed in this way is not changed by the change of the mask pattern process and is self-aligned to the word line. Hence, this process is typically called a self-aligned source process (xe2x80x9cSAS processxe2x80x9d).
FIGS. 7A to 8B are sectional views for explaining a method for fabricating the NOR flash memory device as described above. Here, FIGS. 7A and 8A are sectional views taken along line c-cxe2x80x2 of FIG. 6, while FIGS. 7B and 8B are sectional views taken along line d-dxe2x80x2 of FIG. 6.
Referring to FIGS. 7A and 7B, the field oxide film 52 is formed over the semiconductor substrate 50 by an isolation process such as a local oxidation of silicon (xe2x80x9cLOCOSxe2x80x9d) process, thus dividing the substrate 50 into an active region and a field region. Subsequently, a tunnel oxide film 54 is formed over the active region of the substrate 50 and a first polysilicon layer 56 acting as a floating gate is deposited thereon. Next, the first polysilicon layer 56 on the field oxide film 52 is etched by photolithography, thus separating the floating gate of each cell in the bit line direction. An ONO (oxide/nitride/oxide) layer 58 as an interpoly dielectric layer is formed over the resultant structure and a second polysilicon layer 60 acting as a control gate and an oxide film 62 are sequentially deposited thereon. Subsequently, a photoresist pattern (not shown) for forming word lines is formed over the oxide film 62, and thereafter, the oxide film 62, the second polysilicon layer 60, the ONO layer 58 and the first polysilicon layer 56 are sequentially etched using the photoresist pattern as an etching mask, thus forming a stacked gate. Here, the oxide film 62 serves to prevent the word line 60 from being damaged by dry etcher while removing the exposed field oxide film 52 in a subsequent SAS process.
To perform the SAS process, after forming a photoresist pattern 63 to open the region where the common source region is to be formed, the field oxide film 52 of the opened region is etched using the photoresist pattern 63 as an etching mask. The opened region is self-aligned to the word line 60. Subsequently, n+ impurity 64 is ion-implanted by using the photoresist pattern 63 as an ion-implantation mask. The ion-implanted n+ impurity 64 is diffused by a subsequent thermal process, thus being provided as a common source region connecting the source regions of adjacent cells in the word line direction.
Referring to FIGS. 8A and 8B, after removing the photoresist pattern 63, an xe2x88x92 impurity is ion-implanted by using a mask (not shown) to open a high voltage transistor region in a peripheral circuit region for driving cells. In this case, the source region of the cell is also opened to be ion-implanted by the xe2x88x92 impurity. Next, n+ impurity is ion-implanted to form an NMOS transistor at the peripheral circuit region for driving cells, thus forming the source/drain regions (not shown) of the NMOS transistor. In this case, the cell region is also opened to be ion-implanted by the n+ impurity. As a result, the source region of the cell is formed to be a DD structure of the xe2x88x92 junction and the n+ junction, while the drain region of the cell is formed of only the n+ junction. Here, by ion-implanting xe2x88x92 impurities into the source region of the opened cell during the SAS process, the mask used for making the source region be a DD junction structure may be omitted in a subsequent process. In this case, however, the peripheral circuit region should generate a high voltage of about 12V to be induced to the cell region and provide the high voltage to the source region of the cell requiring this high voltage at a necessary time by a selective switching, and thus the transistor of the peripheral circuit region should be formed to be a junction structure which can endure the high voltage of about 12V. Hence, the typical way of operating this is to open the source region of the cell as well as the high voltage transistor region of the peripheral circuit region after the SAS process and then to ion-implant xe2x88x92 impurity onto the opened source region and high voltage transistor region. Furthermore, to solve the problem that the number of processes in a fabrication method is increased by the SAS process and the xe2x88x92 impurity ion-implantation process, a method may be used which forms the source region of the cell to be an n+ junction structure like the drain region and then removes the high voltage path by lowering the voltage applied to the source region to about 5V and applying a negative voltage to the gate during the erasing operation.
Subsequently, a high temperature oxide (HTO) film 68 and a BPSG (boro-phosphor silicate glass) layer 70 are sequentially deposited over the resultant structure and then the BPSG layer 70 is planarized by a reflow process. The layers deposited over the drain region 66b of the cell are removed by wet and dry etching processes, thus forming a bit line contact 72. A metal layer is deposited over the resultant structure and patterned by a photolithography, thus forming a bit line 74 which is electrically connected to the drain region 66b of the cell via the bit line contact 72.
The conventional method as described above has a problem that an additional mask (reference numeral 63 in FIGS. 7A and 7B) is added to perform the SAS process. Furthermore, all of the oxide film 62 of the exposed region are removed and only the oxide film 62 of the unexposed region close to the bit line contact 72 remains. Because the wet etching should be performed first to improve the contact profile in a subsequent contact process, the distance e between the HTO layer 68 under the BPSG layer 70 and the bit line 74 is reduced. Furthermore, if the HTO layer 68 is exposed in the wet etching process, the HTO layer 68 may then be etched rapidly due to its high wet etching rate and the insulating capability between the word line 60 and the bit line 74 may be degraded, thus causing a malfunction during the cell operation. Therefore, it is necessary to secure a specific distance between the HTO layer 68 and the bit line 74. However, this leads to an increase in the design rule by the thickness of the oxide film 62 formed on the word line 60, thus limiting the reduction in cell size.
Accordingly, an object of the present invention is to provide a method for manufacturing a nonvolatile memory device using an SAS process that can secure a process margin at a bit line contact region without the use of an additional mask, to solve the problems depicted above.
To achieve the above object, a nonvolatile memory device is provided, comprising: a memory cell array having a plurality of cells, each cell including a stacked gate, a source region, and a drain region formed over a substrate in the vicinity of the stacked gate, wherein the stacked gate includes a floating gate, a control gate, and an interdielectric layer interposed between the floating gate and the control gate, a word line provided in a row to connect the control gates of the cells, a common source region formed in the substrate in parallel with the word line to connect the source regions of the cells, and a field insulating layer formed between the cells, having side edges formed in a self-alignment manner with side edges of the word line. Preferably, the field insulating layer is not formed in an area between the drain regions of the cells.
To achieve the above object, there is also provided a method for manufacturing a nonvolatile memory device comprising a memory cell array having a plurality of cells, the method comprising forming a field oxide film over a semiconductor substrate to define an active region of the substrate, sequentially forming a tunnel oxide film, a first conductive layer, an interpoly dielectric layer, a second conductive layer, and a first insulating layer over the substrate, forming a stacked gate of the first and second conductive layers over the active region, forming source/drain regions of a first concentration by ion-implanting a first impurity in a portion of the active region exposed by the stacked gate, removing an exposed portion of the field oxide film using the second conductive layer as an etching mask, and exposing the source region of each cell and a portion of the second conductive layer, and ion-implanting second impurity using the exposed second conductive layer as a mask.
In this method, the second conducting layer may be used as a word line. Preferably all of the first insulating layer is etched in the step of removing the exposed field oxide film. The first insulating layer preferably remains over the whole of the second conductive layer and maintains a uniform thickness after the step of removing the exposed field oxide film.
To achieve the above object, there is provided yet another method for manufacturing a nonvolatile memory device comprising a memory cell array having a plurality of cells, each cell including a stacked gate structure having a first conductive layer and a second conductive layer, and a peripheral circuit region for driving the cells, the method comprising: forming a field oxide film over a semiconductor substrate to define an active region of the substrate, sequentially forming a tunnel oxide film, the first conductive layer, an interpoly dielectric layer, the second conductive layer and a first insulating layer over the substrate, forming a single-layer gate comprising the second conductive layer over the active region of the peripheral circuit region, forming a stacked gate of the first and second conductive layers over the active region of the memory cell array, forming source/drain regions of the cell at a first concentration by ion-implanting a first impurity in a portion of the active region of the memory cell array that is exposed by the stacked gate, removing an exposed portion of the field oxide film using the second At conductive layer as an etching mask, and exposing the source region of each cell in the memory cell array and an active region of the peripheral circuit region and ion-implanting a second impurity in the exposed source regions.
The second conducting layer may be used as a word line. Preferably the steps of forming a stacked gate, forming source/drain regions of the cell at a first concentration, and removing an exposed portion of the field oxide film are all processed using a single photo mask.
The step of sequentially forming a tunnel oxide film, the first conductive layer, an interpoly dielectric layer, the second conductive layer and a first insulating layer over the substrate, may further comprises isolating the first conductive layer of each cell by exposing a portion of the field oxide film between the active regions of the memory cell array and etching the first conductive layer, the isolating being performed before forming the interpoly dielectric layer over the first conductive layer. The step of sequentially forming a tunnel oxide film, the first conductive layer, an interpoly dielectric layer, the second conductive layer and a first insulating layer over the substrate, may also comprise removing the interpoly dielectric layer and the first conductive layer in the peripheral circuit region, and forming a gate oxide film over the active region of the peripheral circuit region, before forming the second conductive layer over the interpoly dielectric layer.
Preferably all portions of the first insulating layer are etched in the step of removing the exposed oxide film. Also, the first insulating layer preferably remains over the whole of the second conductive layer and maintains a uniform thickness after the step of removing the exposed oxide film.
This method may further comprise forming an impurity region of a second concentration lower than the first concentration by exposing the source region of the cell and ion-implanting a third impurity into the exposed source region of the cell. This may be done either before or after the step of exposing the source region of each cell in the memory cell array and an active region of the peripheral circuit region and ion-implanting a second impurity in the exposed source regions. Preferably, a region where a high voltage device is to be formed in the peripheral circuit region is also exposed when exposing the source region of the cell.
As described above, the present invention does not need an additional mask for SAS process because the SAS process is performed by using the mask for forming the stacked gate of the memory cell array. Furthermore, this makes it possible to secure sufficient process margin in the bit line contact region, since all portions of the first insulating layer on the word line are removed or remain while maintaining a uniform thickness after the SAS etching process.